The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Apr. 01, 2005
Andrew P. Hoover, Austin, TX (US);
Brian M. Millar, Austin, TX (US);
Milind P. Padhye, Austin, TX (US);
Andrew P. Hoover, Austin, TX (US);
Brian M. Millar, Austin, TX (US);
Milind P. Padhye, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A flip-flop () has a normal mode and a low power mode to save power. The flip-flop () has a master latch () and a slave latch (). The slave latch () is used to retain the condition of the flip-flop () during the low power mode, where power is withdrawn from the master latch () but maintained on the slave latch (). The slave latch () may use transistors with lower leakage characteristics than the transistors that make up the master latch (). These lower leakage characteristics may be achieved by a higher threshold voltage and/or a thicker gate dielectric. Operating speed of the flip-flop () is maintained by implementing the slave latch () so that no logic gate or switching transistor is in the critical timing path. Instead, the slave latch () has an input/output terminal to tap into the signal path between the master latch and an output circuit ().