The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Jun. 19, 2003
Binan Wang, Tucson, AZ (US);
Paul Stulik, Tucson, AZ (US);
Binan Wang, Tucson, AZ (US);
Paul Stulik, Tucson, AZ (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A voltage monitor circuit for biasing a well region of a CMOS circuit includes a self-biased comparator which compares first (INP) and second (INN) input signals. The comparator includes first (MN) and second (MN) N-channel transistors with grounded sources, a drain of the first N-channel transistor and a gate of the second N-channel transistor being coupled to a first output (OUTN), and a drain of the second N-channel transistor and a gate of the first N-channel transistor being coupled to a second output (OUTP). First (MP) and second (MP) P-channel transistors are operated to couple the second or first input signal to the second or first output, respectively, by controlling the gate-to-source voltage of the first or second P-channel transistor according to the polarity of a voltage difference between the first and second input signals.