The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Mar. 22, 2005
James Schleicher, Santa Clara, CA (US);
Jim Park, San Jose, CA (US);
Sergey Shumarayev, San Leandro, CA (US);
Bruce Pederson, San Jose, CA (US);
Tony Ngai, Campbell, CA (US);
Wei-jen Huang, Burlingame, CA (US);
Victor Maruri, Mountain View, CA (US);
Rakesh Patel, Cupertino, CA (US);
James Schleicher, Santa Clara, CA (US);
Jim Park, San Jose, CA (US);
Sergey Shumarayev, San Leandro, CA (US);
Bruce Pederson, San Jose, CA (US);
Tony Ngai, Campbell, CA (US);
Wei-Jen Huang, Burlingame, CA (US);
Victor Maruri, Mountain View, CA (US);
Rakesh Patel, Cupertino, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.