The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2006
Filed:
Dec. 03, 2004
Masachika Masuda, Tokorozawa, JP;
Tamaki Wada, Higashimurayama, JP;
Michiaki Sugiyama, Tokyo, JP;
Hirotaka Nishizawa, Kokubunji, JP;
Toshio Sugano, Kodaira, JP;
Yasushi Takahashi, Urawa, JP;
Masayasu Kawamura, Higashiyamato, JP;
Masachika Masuda, Tokorozawa, JP;
Tamaki Wada, Higashimurayama, JP;
Michiaki Sugiyama, Tokyo, JP;
Hirotaka Nishizawa, Kokubunji, JP;
Toshio Sugano, Kodaira, JP;
Yasushi Takahashi, Urawa, JP;
Masayasu Kawamura, Higashiyamato, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi Ulsi Systems Co., Ltd., Tokyo, JP;
Abstract
A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.