The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7122417 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 17, 2006

Filed:

Feb. 10, 2004
Applicant:

Dong-soo Chang, Kyungki-do, KR;

Inventor:

Dong-Soo Chang, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 1/336 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
Abstract

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is fabricated by forming gate spacers on both sidewalls of a gate pattern in a semiconductor substrate including first and second regions. Then, a first impurity region is formed in the semiconductor substrate at the first region, and the gate spacer exposed at the first region is removed. A second impurity region is formed in the semiconductor substrate at the first region. A third impurity region is formed at the semiconductor substrate in the second region, and the gate spacer exposed at the second region is removed. A fourth impurity region is formed in the semiconductor substrate at the second region. The first and third impurity regions are formed deeper than the second and fourth impurity regions.


Find Patent Forward Citations

Chang, Dong-Soo. (2006). Methods for fabricating metal-oxide-semiconductor field effect transistors using gate sidewall spacers (U.S. Patent No. 7122417). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7122417

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