The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Sep. 24, 2002
Takao Toi, Minato-ku, JP;
Toru Awashima, Minato-ku, JP;
Yoshiyuki Miyazawa, Kawasaki, JP;
Noritsugu Nakamura, Minato-ku, JP;
Taro Fujii, Minato-ku, JP;
Koichiro Furuta, Minato-ku, JP;
Masato Motomura, Minato-ku, JP;
Takao Toi, Minato-ku, JP;
Toru Awashima, Minato-ku, JP;
Yoshiyuki Miyazawa, Kawasaki, JP;
Noritsugu Nakamura, Minato-ku, JP;
Taro Fujii, Minato-ku, JP;
Koichiro Furuta, Minato-ku, JP;
Masato Motomura, Minato-ku, JP;
NEC Corporation, Tokyo, JP;
Abstract
An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.