The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2006

Filed:

Feb. 05, 2003
Applicants:

Yong-deok Kim, Seoul, KR;

Yun-je OH, Yongin-shi, KR;

Jun-ho Koh, Suwon-shi, KR;

Han-lim Lee, Seoul, KR;

Byung-jik Kim, Songnam-shi, KR;

Chan-youl Kim, Puchon-shi, KR;

Inventors:

Yong-Deok Kim, Seoul, KR;

Yun-Je Oh, Yongin-shi, KR;

Jun-Ho Koh, Suwon-shi, KR;

Han-Lim Lee, Seoul, KR;

Byung-Jik Kim, Songnam-shi, KR;

Chan-Youl Kim, Puchon-shi, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The provided forward error correction (FEC) apparatus for a transmission system includes a low pass filter (LPF) passing only a low frequency component of an input signal having a predetermined transmission rate; an AC power meter converting an energy value of an signal output from the LPF into a DC voltage value; a logarithm amplifier converting the exponentially varying DC voltage value from the AC power meter into a linear logarithmically varying DC voltage value; a digital signal processor (DSP) determining the transmission rate of the input signal according to a magnitude of the linear DC voltage value and outputting a control signal according to the transmission rate; a clock generator receiving the control signal and generating a clock signal according to the control signal; and a FEC module receiving the clock signal and performing FEC operation on the received signal. A method for FEC is also provided.


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