The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Oct. 03, 2003
Atsushi Miyairi, Tokyo, JP;
Shinichi Numata, Kanagawa, JP;
Katsuhiro Hashimoto, Tokyo, JP;
Shojiro Sato, Kanagawa, JP;
Takaaki Morimura, Tokyo, JP;
Masataka Suzuki, Tokyo, JP;
Soichi Sato, Tokyo, JP;
Tamaki Kojima, Tokyo, JP;
Hidenori Yamaji, Tokyo, JP;
Atsushi Miyairi, Tokyo, JP;
Shinichi Numata, Kanagawa, JP;
Katsuhiro Hashimoto, Tokyo, JP;
Shojiro Sato, Kanagawa, JP;
Takaaki Morimura, Tokyo, JP;
Masataka Suzuki, Tokyo, JP;
Soichi Sato, Tokyo, JP;
Tamaki Kojima, Tokyo, JP;
Hidenori Yamaji, Tokyo, JP;
Sony Corporation, Tokyo, JP;
Abstract
Performing power saving control which can be inherited and standardized easily, and which keeps power devices from having to become larger is made possible. A current In flowing through an electrical path is detected as a voltage Vs by a current detection section, and is outputted as a voltage Vout by an amplifying section. When a level corresponding to the voltage Vout exceeds a limit level, a power limit detection section outputs a power limit detection signal. When a controller receives the power limit detection signal via a detection signal holding section, the controller outputs a throttle control command signal. When a chip set receives the throttle control command signal, the chip set initiates throttle control that lowers the clock frequency of a CPU. The present invention may be applied to laptop personal computers.