The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2006

Filed:

Dec. 11, 2003
Applicants:

Sweyyan Shei, Cupertino, CA (US);

Ming Yang Wang, LaFayette, CA (US);

Vincent Chiu, Fremont, CA (US);

Neu Choo Ngui, Fremont, CA (US);

Inventors:

Sweyyan Shei, Cupertino, CA (US);

Ming Yang Wang, LaFayette, CA (US);

Vincent Chiu, Fremont, CA (US);

Neu Choo Ngui, Fremont, CA (US);

Assignee:

Fortelink, Inc., Fremont, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A resource board for a circuit emulator holds programmable logic devices (PLDs) and other emulation resources such as random access memories (RAMs) and employs both hard-wired and network-based virtual signal paths to flexibly route signals between the emulation resources on the resource board and resources mounted on other resource boards, workstations and other external equipment. The resource board also provides the logic and balanced signal paths needed to deliver clock signals to the PLDs and reduces the number of signals needed to communicate with external test equipment by implementing much of the pattern generation and data acquisition functionality needed to test an emulated circuit.


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