Apparatus and method for on-chip jitter measurement

Abstract

A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an input and an output that produces a delayed version of the signal at the input. The first set of circuitry is configured to detect propagation of the significant instant of the input clock signal through each of the delay elements and produces a pulse in response thereto. The width of the pulse is approximately equal to the delay of the corresponding delay element. The second set of circuitry has one storage element corresponding to each output of the first set of circuitry, for receiving a trigger signal that is timed to correspond to a delay which is approximately half of the total delay of the chain, and for recording in the corresponding storage element any pulse that is active at the time of occurrence of the trigger signal. Thus, a jitter measurement is made based on the pulses recorded in the storage elements after a plurality of trigger signals has occurred.