The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Aug. 31, 2004
Martin Versen, Munich, DE;
Klaus Nierle, Essex Junction, VT (US);
Martin Versen, Munich, DE;
Klaus Nierle, Essex Junction, VT (US);
Infineon Technologies AG, Munich, DE;
Abstract
DRAM memory device () comprising at least one array of memory cells (), each memory cell () being connected to a bit line (BL) and a word line (WL), each of said bit lines (BL) being connected to a sense amplifier and a pre-charge circuit (); a controllable active-current generator () for providing power to the sense amplifiers and pre-charge circuits () for a time interval that is limited by a time at which a command for a read or write access is applied to the DRAM memory device () and an assigned switching time; a controllable standby-current generator () for providing power to the sense amplifiers and pre-charge circuits () after the switching time; a control circuit () for receiving external data, address and control signals (C, A, D) and for controlling the active-current generator () and the standby-current generator (); wherein the control circuit () is adapted to control the time for switching the respective power generator () to the sense amplifiers and to the pre-charge circuits () subject to an external test mode signal for reducing the overall testing time in a test of the serviceability of the bit lines (BL), sense amplifiers and pre-charge circuits ().