The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2006

Filed:

Nov. 18, 2005
Applicant:

Takahiro Yoshino, Kasugai, JP;

Inventor:

Takahiro Yoshino, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

To present a control circuit of a DC—DC converter to be incorporated in a logic circuit, having a digital error amplifier capable of controlling the gain depending on an input voltage and an output voltage, without requiring a resistance or a capacitor of high precision used in a feedback circuit or the like. A ΣΔ AD converter type error amplifierincludes an arithmetic unit, an integrating unit, a 1-bit quantizing unit, a D/A converter, and a first counter. The arithmetic unitoutputs a differential signal of an output voltage Vout and an average output voltage AV. The integrating unitoutputs an integral signal by integrating the differential signal. The 1-bit quantizing unitoutputs a 1-bit digital signal by quantizing the integral signal. The D/A converterconverts from digital to analog depending on a 1-bit digital signal. A digital PWM circuitdetermines the on-duty of the main switching element of the DC—DC converter depending on the pulse density of the D/A converter


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