The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Jun. 30, 2004
Hyung Soon Park, Gyeonggi-do, KR;
Min Suk Lee, Gyeonggi-do, KR;
Sang Ick Lee, Gyeonggi-do, KR;
Hyun Chul Sohn, Gangnam-gu, KR;
Hyung Soon Park, Gyeonggi-do, KR;
Min Suk Lee, Gyeonggi-do, KR;
Sang Ick Lee, Gyeonggi-do, KR;
Hyun Chul Sohn, Gangnam-gu, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
Disclosed is a method for forming a polysilicon plug of a semiconductor device. The method comprises the steps of: forming a stacked pattern of a wordline and a hard mask film on a semiconductor substrate comprising a cell region and a peripheral circuit region; forming a spacer on a sidewall of the stacked pattern; forming an interlayer insulating film on the semiconductor substrate; polishing the interlayer insulating film via a CMP process using the hard mask film as a polishing barrier film; forming a barrier film on the semiconductor substrate including the interlayer insulating film; selectively etching the barrier film and the interlayer insulating film to form a landing plug contact hole; depositing a polysilicon film filling the landing plug contact hole on the semiconductor substrate; blanket-etching the polysilicon film using the barrier film as an etching barrier film; and polishing the polysilicon film and the barrier film using the hard mask film as a polishing barrier film to form a polysilicon plug.