The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2006

Filed:

May. 17, 2005
Applicants:

Joseph A. Yedinak, Mountaintop, PA (US);

Dwayne S. Reichl, Pocono Lake, PA (US);

Douglas J. Lange, Mountaintop, PA (US);

Inventors:

Joseph A. Yedinak, Mountaintop, PA (US);

Dwayne S. Reichl, Pocono Lake, PA (US);

Douglas J. Lange, Mountaintop, PA (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.


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