The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Oct. 22, 2004
Huimou Juliana LI, Sunnyvale, CA (US);
Mehul R. Vashi, San Jose, CA (US);
Qingqi Wang, San Jose, CA (US);
Andy H. Gan, San Jose, CA (US);
Huimou Juliana Li, Sunnyvale, CA (US);
Mehul R. Vashi, San Jose, CA (US);
Qingqi Wang, San Jose, CA (US);
Andy H. Gan, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded circuit, a hardware description language (HDL) pin name from an HDL description of the embedded circuit, a schematic pin name of the second circuit to which a corresponding pin in the embedded circuit is to connect, a signal direction associated with the pin, and a name of a clock to trigger a signal on the pin. A plurality of design views are generated from the master file. Each design view has a unique format relative to the other design views and includes for each pin in the embedded circuit design, at least the HDL pin name, the associated schematic pin name, and a signal direction associated with the pin.