The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Oct. 11, 2001
Applicants:

Max M. Yeung, San Jose, CA (US);

Richard J. Stephani, St. Paul, MN (US);

Miguel A. Vilchis, San Jose, CA (US);

Inventors:

Max M. Yeung, San Jose, CA (US);

Richard J. Stephani, St. Paul, MN (US);

Miguel A. Vilchis, San Jose, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.


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