The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Jul. 31, 2003
Applicant:
Sven Boldt, Aschheim, DE;
Inventor:
Sven Boldt, Aschheim, DE;
Assignee:
Infineon Technologies AG, Munich, DE;
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A testing method involves information being written to memory addresses and being read from the memory addresses. The method which logically combines parallel memory bank actuation of the memory addresses using an interleaved mode, which is implemented in relation to disjunct subareas of the memory banks, with one another. This shortens the test time required for testing the semiconductor memory.
Boldt, Sven. (2006). Method for testing a semiconductor memory having a plurality of memory banks (U.S. Patent No. 7117407). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7117407
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