The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Nov. 28, 2000
Applicants:

Stephen M. Trimberger, San Jose, CA (US);

Raymond C. Pang, San Jose, CA (US);

Walter N. Sze, Saratoga, CA (US);

Jennifer Wong, Fremont, CA (US);

Inventors:

Stephen M. Trimberger, San Jose, CA (US);

Raymond C. Pang, San Jose, CA (US);

Walter N. Sze, Saratoga, CA (US);

Jennifer Wong, Fremont, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 9/14 (2006.01); H04K 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.


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