The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Feb. 18, 2004
Applicants:

Paresh Chatterjee, Fremont, CA (US);

Chayan Biswas, Newark, CA (US);

Ragendra Mishra, Fremont, CA (US);

Senthil Thangaraj, Fremont, CA (US);

Inventors:

Paresh Chatterjee, Fremont, CA (US);

Chayan Biswas, Newark, CA (US);

Ragendra Mishra, Fremont, CA (US);

Senthil Thangaraj, Fremont, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.


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