The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Feb. 27, 2004
Hans Jurgen Mattausch, Higashihiroshima, JP;
Tetsushi Koide, Higashihiroshima, JP;
Tetsuo Hironaka, Hiroshima, JP;
Hiroshi Uchida, Ogori, JP;
Koh Johguchi, Hiroshima, JP;
Zhaomin Zhu, Higashihiroshima, JP;
Hans Jurgen Mattausch, Higashihiroshima, JP;
Tetsushi Koide, Higashihiroshima, JP;
Tetsuo Hironaka, Hiroshima, JP;
Hiroshi Uchida, Ogori, JP;
Koh Johguchi, Hiroshima, JP;
Zhaomin Zhu, Higashihiroshima, JP;
Semiconductor Technology Academic Research Center, Kanagawa, JP;
Abstract
In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.