The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Aug. 28, 2001
Applicant:
Qiyong Bian, Hillsboro, OR (US);
Inventor:
Qiyong Bian, Hillsboro, OR (US);
Assignee:
Other;
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/54 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A Verilog/PLI module that simulates behavior of an electronic system is co-simulated in a clock-accurate manner with a System C module that models the behavior of a component of the electronic system using a remote procedure call (RPC). Adding RPC functionality to the Verilog/PLI and System C modules facilitates exchanging parameters between the modules. The RPC is used to transfer process control to the SystemC module, after execution of which control is returned to the Verilog/PLI module. A return value is also returned to the Verilog/PLI module; this return value represents output signals associated with the System C module.