The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
May. 30, 2002
Alexander Hoefler, Austin, TX (US);
Chi Nan Brian LI, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Alexander Hoefler, Austin, TX (US);
Chi Nan Brian Li, Austin, TX (US);
Gowrishankar L. Chindalore, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate () by forming elevated sources and drains () in contact with extensions () within the top silicon layer () of the SOI substrate (). Buried conductive regions () are formed within the top silicon layer () below the extensions () to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (), extensions () and the buried conductive regions () in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (), extensions () and the buried conductive regions ().