The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Nov. 18, 2005
Hyun Cheol Bae, Daejeon, KR;
Seung Yun Lee, Daejeon, KR;
Sang Hun Kim, Daejeon, KR;
Jin Yeong Kang, Daejeon, KR;
Hyun Cheol Bae, Daejeon, KR;
Seung Yun Lee, Daejeon, KR;
Sang Hun Kim, Daejeon, KR;
Jin Yeong Kang, Daejeon, KR;
Electronics and Telecommunications Research Institute, Daejeon, KR;
Abstract
Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.