The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2006

Filed:

Apr. 28, 2004
Applicants:

Takatoshi Tsujimura, Fujisawa, JP;

Osamu Tokuhiro, Shiga-ken, JP;

Mitsuo Morooka, Kawasaki, JP;

Takashi Miyamoto, Chofu, JP;

Inventors:

Takatoshi Tsujimura, Fujisawa, JP;

Osamu Tokuhiro, Shiga-ken, JP;

Mitsuo Morooka, Kawasaki, JP;

Takashi Miyamoto, Chofu, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film, a gate insulating filmand a gate electrode are sequentially stacked on an insulating substrate. The amorphous silicon filmincludes a low defect-density amorphous silicon layerformed at a low deposition rate and a high deposition rate amorphous silicon layerformed at a deposition rate higher than that of the low defect-density amorphous silicon layer. The low defect-density amorphous silicon layerin the amorphous silicon filmis grown closer to the insulating substrate, and the high deposition rate amorphous silicon layeris grown closer to the gate insulating film


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