The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2006

Filed:

Oct. 21, 2003
Applicants:

Tatsuya Kanda, Kawasaki, JP;

Akihiro Funyu, Kawasaki, JP;

Takahiko Sato, Kawasaki, JP;

Yoshiaki Okuyama, Kawasaki, JP;

Jun Ohno, Kawasaki, JP;

Hitoshi Ikeda, Kawasaki, JP;

Inventors:

Tatsuya Kanda, Kawasaki, JP;

Akihiro Funyu, Kawasaki, JP;

Takahiko Sato, Kawasaki, JP;

Yoshiaki Okuyama, Kawasaki, JP;

Jun Ohno, Kawasaki, JP;

Hitoshi Ikeda, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory includes a refresh timer and an arbiter for determining the order of precedence between an access operation and a refresh operation, in order to automatically perform refresh operations inside the memory. A detecting circuit operates in a test mode and outputs a detection signal indicating that the refresh operation is yet to be performed, when a new internal refresh request occurs before the refresh operation is performed. For example, the detection signal is output when the interval of access requests is short and no refresh operation can be inserted between the access operations. That is, in the semiconductor memory in which refresh operations are performed automatically, it is possible to evaluate the minimum interval of supplying access requests. As a result, the evaluation time can be reduced with a reduction in the development period of the semiconductor memory.


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