The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2006
Filed:
Nov. 12, 2004
Richard B. Brown, Salt Lake City, UT (US);
Gary D. Carpenter, Austin, TX (US);
Fadi H. Gebara, Macomb, MI (US);
Richard B. Brown, Salt Lake City, UT (US);
Gary D. Carpenter, Austin, TX (US);
Fadi H. Gebara, Macomb, MI (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.