The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2006
Filed:
Sep. 08, 2005
Bevin George Perumana, Atlanta, GA (US);
Sudipto Chakraborty, Atlanta, GA (US);
Chang-ho Lee, Marietta, GA (US);
Joy Laskar, Marietta, GA (US);
Sang-hyun Woo, Seoul, KR;
Bevin George Perumana, Atlanta, GA (US);
Sudipto Chakraborty, Atlanta, GA (US);
Chang-Ho Lee, Marietta, GA (US);
Joy Laskar, Marietta, GA (US);
Sang-Hyun Woo, Seoul, KR;
Samsung Electronics Co., Ltd., , KR;
Georgia Tech Research Corporation, Atlanta, GA (US);
Abstract
A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.