The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2006

Filed:

Dec. 22, 2004
Applicants:

Shekhar Bhansali, Tampa, FL (US);

Shyam Aravamudhan, Tampa, FL (US);

Kevin Luongo, St. Petersburg, FL (US);

Sunny Kedia, Tampa, FL (US);

Inventors:

Shekhar Bhansali, Tampa, FL (US);

Shyam Aravamudhan, Tampa, FL (US);

Kevin Luongo, St. Petersburg, FL (US);

Sunny Kedia, Tampa, FL (US);

Assignee:

University of South Florida, Tampa, FL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method for the synthesis of nanowires in a silicon nanoporous template by electrodeposition and a novel technique for the integration of nanowires to transduction surfaces. In accordance with the present invention, a method for the fabrication of nanowire interconnects is provided. The method includes the steps of fabricating substantially vertical nanowires in a selectively passivated nanoporous silicon template, backetching the silicon template to expose the nanowires, eutectically bonding the exposed nanowires to a receiving silicon wafer, and etching the silicon template to produce substantially freestanding nanowire interconnects in contact with the receiving silicon wafer.


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