The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2006

Filed:

Jul. 22, 2005
Applicants:

Shanjen Pan, Plano, TX (US);

James R. Todd, Plano, TX (US);

Sameer Pendharkar, Allen, TX (US);

Inventors:

Shanjen Pan, Plano, TX (US);

James R. Todd, Plano, TX (US);

Sameer Pendharkar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A CMOS integrated circuit (A-B-C) includes both relatively low-power () and high-power () CMOS transistors on the same chip. A 20V, relatively high-power PMOS device () includes a heavily doped N-well drain region (). A 20V, relatively high-power NMOS device () includes heavily doped P-type buried layers () underneath the source () and drain regions () and spanning the gap between the P-well gate (F) and adjacent P-well isolation regions ().


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