The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2006

Filed:

Jul. 03, 2003
Applicants:

Satish R. Ganesan, Mountain View, CA (US);

Sundararajarao Mohan, Sunnyvale, CA (US);

Ralph D. Wittig, Menlo Park, CA (US);

Inventors:

Satish R. Ganesan, Mountain View, CA (US);

Sundararajarao Mohan, Sunnyvale, CA (US);

Ralph D. Wittig, Menlo Park, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.


Find Patent Forward Citations

Ganesan, Satish. (2006). Softpal implementation and mapping technology for fpgas with dedicated resources (U.S. Patent No. 7111273). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7111273

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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