The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2006
Filed:
Sep. 30, 2003
Amit Singh, San Jose, CA (US);
Amit Singh, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method () of physical circuit design can include the steps of packing components () of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations () to each component of the circuit design. The components of the circuit design can be clustered () by combining slices and including slices into configurable logic blocks according to design constraints, while leaving enough white space in the configurable logic blocks for post-placement circuit optimizations. The components of the circuit design then can be placed () to minimize critical connections. The circuit design can be declustered () to perform additional placer optimization tasks () on the declustered circuit design.