Bi-directional serializer/deserializer with discretionary loop-back

Abstract

A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r≧s.