The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2006
Filed:
Oct. 29, 2002
Suzanne C. Martin, Altadena, CA (US);
Christopher J. Rollison, San Juan Capistrano, CA (US);
Blythe C. Deckman, Corona, CA (US);
James J. Rosenberg, Monrovia, CA (US);
Suzanne C. Martin, Altadena, CA (US);
Christopher J. Rollison, San Juan Capistrano, CA (US);
Blythe C. Deckman, Corona, CA (US);
James J. Rosenberg, Monrovia, CA (US);
Wavestream Wireless Technologies, San Dimas, CA (US);
Abstract
The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.