The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2006

Filed:

Nov. 15, 2004
Applicants:

Xeujun Yuan, San Jose, CA (US);

YE Xiong, San Jose, CA (US);

Peter F. Lai, San Jose, CA (US);

Inventors:

Xeujun Yuan, San Jose, CA (US);

Ye Xiong, San Jose, CA (US);

Peter F. Lai, San Jose, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.


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