The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2006
Filed:
Dec. 18, 2003
Xiao-jie Yuan, Sunnyvale, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Zicheng G. Ling, San Jose, CA (US);
Steven P. Young, Boulder, CO (US);
Xiao-Jie Yuan, Sunnyvale, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Zicheng G. Ling, San Jose, CA (US);
Steven P. Young, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.