The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7107477 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 12, 2006

Filed:

Jan. 31, 2003
Applicants:

Deshanand Singh, Mississauga, CA;

Andrew Hall, High Wycombe, GB;

Inventors:

Deshanand Singh, Mississauga, CA;

Andrew Hall, High Wycombe, GB;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.


Find Patent Forward Citations

Singh, Deshanand. (2006). Programmable logic devices with skewed clocking signals (U.S. Patent No. 7107477). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7107477

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…