The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Sep. 05, 2001
Applicant:

Laurent Stadler, San Francisco, CA (US);

Inventor:

Laurent Stadler, San Francisco, CA (US);

Assignee:

XILINX, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data transfer request. A bus master unit (BMU) is coupled with the CSL through the first set of signal lines and the second set of signal lines. The BMU is connected to the CSI bus. The BMU arbitrates to take control of the CSI bus on behalf of the CSL enabling the CSL to perform data transfer to or from the CSI bus bypassing the processor.


Find Patent Forward Citations

Stadler, Laurent. (2006). Method for bus mastering for devices resident in configurable system logic (U.S. Patent No. 7107374). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7107374

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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