Method and apparatus for reducing latency in a digital signal processing device

Abstract

A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith. The processing circuitry is operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.