The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Apr. 11, 2000
Applicants:

Brian Mitchell Bass, Apex, NC (US);

Jean Louis Calvignac, Cary, NC (US);

Anthony Matteo Gallo, Apex, NC (US);

Marco C. Heddes, Raleigh, NC (US);

Michael Steven Siegel, Raleigh, NC (US);

Fabrice Jean Verplanken, La Gaude, FR;

Inventors:

Brian Mitchell Bass, Apex, NC (US);

Jean Louis Calvignac, Cary, NC (US);

Anthony Matteo Gallo, Apex, NC (US);

Marco C. Heddes, Raleigh, NC (US);

Michael Steven Siegel, Raleigh, NC (US);

Fabrice Jean Verplanken, La Gaude, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.


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