The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2006

Filed:

Apr. 01, 2005
Applicants:

Pierangelo Confalonieri, Caponago, IT;

Marco Zamprogno, Cesano Maderno, IT;

Francesca Girardi, Milan, IT;

Inventors:

Pierangelo Confalonieri, Caponago, IT;

Marco Zamprogno, Cesano Maderno, IT;

Francesca Girardi, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means. Also described is a method of using the converter that comprises the following phases: loading of the analog quantity in the quantization means, memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means.


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