The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7103488 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 05, 2006

Filed:

Jul. 16, 2004
Applicants:

David Goren, Nesher, IL;

John Katzenstein, Chicago, IL (US);

Youri V. Tretiakov, South Burlington, VT (US);

Inventors:

David Goren, Nesher, IL;

John Katzenstein, Chicago, IL (US);

Youri V. Tretiakov, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for detemiining fringing capacitances on passive devices within an integrated circuit is disclosed. A fringing capacitance region on a passive device is initially divided into a group of fringing electric field areas. A set of fringing capacitance equations is then developed for the fringing electric field areas accordingly. A determination is made as to whether or not an accuracy of the fringing capacitance equations meets a predetermined threshold. If so, then the fringing capacitance equations are utilized in compact device models to determine fringing capacitance on the passive device; otherwise, the physically-based fringing capacitance equations are fitted to a set of extracted data to generate a refined set of physically-based fringing capacitance equations, and the refined set of physically-based fringing capacitance equations is utilized in compact device models to determine fringing capacitance on the passive device.


Find Patent Forward Citations

Goren, David. (2006). Method for determining fringing capacitances on passive devices within an integrated circuit (U.S. Patent No. 7103488). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7103488

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