System and method for half-rate clock phase detection

Abstract

A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q; latching Qwith the second clock, creating Q; latching Qwith the first clock, creating Q; XORing Qand Qto create phase signals; and, XORing Qand Qto create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.