Integrated semiconductor memory device and method for operating an integrated semiconductor memory device

Abstract

An integrated semiconductor memory device includes a memory cell array (B) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit () configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A) that applies a mid-voltage (V), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.