The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Jun. 30, 2004
Hon Kin Chiu, Hayward, CA (US);
Hon Kin Chiu, Hayward, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL circuit includes a gated PFD and an equalization pulse removal logic circuit. The equalization pulse removal logic circuit is arranged such that, if equalizing pulses occur in a sync signal, the gated PFD is gated during each equalizing pulse. The second PLL circuit is arranged to provide a wide capture range, and to lock a center of a pulse of the center of the feedback signal with the leading edge of the first PLL output signal. The second PLL circuit includes a frequency comparator circuit, a PFD, and a phase detector. The frequency comparator circuit is arranged to select either the PFD or the phase detector.