Method and system for ensuring the assertion order of signals in a chip independent of physical layout

Abstract

Certain embodiments for ensuring the assertion order of signals in a chip independent of physical layout may comprise receiving a first signal by a first logic block of a plurality of logic blocks integrated within a chip, where the first signal may initiate a reset of a first function within the first logic block. A second signal may be communicated from within the first logic block to a second function within a second logic block of the plurality of logic blocks, and the second signal may be adapted to initiate the second function. The first signal may be the same as a second signal. The reset of the first function may initialize the first function to a known state before the second function may generate an output that may be received by the first function. The first function may place the chip in a test mode when indicated by the generated output of the second function.