The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Jan. 29, 2003
Applicants:

Joannes Christianus Drenth, Mettmenstetten, CH;

Daniel Thommen, Zurich, CH;

Zeljko Mrcarica, Zurich, CH;

Kurt Henggeler, Winterthur, CH;

Inventors:

Joannes Christianus Drenth, Mettmenstetten, CH;

Daniel Thommen, Zurich, CH;

Zeljko Mrcarica, Zurich, CH;

Kurt Henggeler, Winterthur, CH;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01); H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
Abstract

The digital electronic circuit () includes a logic cell () for processing data () , a flip-flop () for storing data () processed in the logic cell (), a power supply (), and a clock () for triggering the flip-flop () . The logic cell () is disconnected from the power supply () when the clock () is not active, as it is not needed for memorizing of the flip-flop states, and connected with the power supply () when the clock () is enabled. For switching the power supply, a switch () switched by the clock enable () is arranged between the logic cell () and the power supply (). Such a simple additional switch () occupies only a relatively small area on the chip, but permits a drastic reduction by about 90% of the leakage currents. The circuit () is especially design and may be used for instance in mobile telecommunication devices.


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