The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Aug. 16, 2004
Applicants:

Chih-feng Huang, Jhubei, TW;

Ta-yung Yang, Milpitas, CA (US);

Jenn-yu G. Lin, Taipei, TW;

Tuo-hsin Chien, Tucheng, TW;

Inventors:

Chih-Feng Huang, Jhubei, TW;

Ta-yung Yang, Milpitas, CA (US);

Jenn-yu G. Lin, Taipei, TW;

Tuo-Hsin Chien, Tucheng, TW;

Assignee:

System General Corp., Taipei Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A high voltage LDMOS transistor according to the present invention includes at least one P-field block in the extended drain region of the N-well. The P-field blocks form junction-fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown occurs. A higher breakdown voltage is therefore achieved and the N-well having a higher doping density is thus allowed. The source region and P-field blocks enclose the drain region, which makes the LDMOS transistor self-isolated.


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