The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2006
Filed:
Apr. 05, 2005
Thierry Coffi Hervé Yao, Oudenaarde, BE;
Greg Scott, Inkom, ID (US);
Pierre André Claude Gassot, Lille, FR;
Philip John Cacharelis, Oudenaarde, BE;
Thierry Coffi Hervé Yao, Oudenaarde, BE;
Greg Scott, Inkom, ID (US);
Pierre André Claude Gassot, Lille, FR;
Philip John Cacharelis, Oudenaarde, BE;
AMI Semiconductor, Inc., Pocatello, ID (US);
Abstract
An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.