The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2006

Filed:

Mar. 22, 2002
Applicants:

Sumio Ohta, Aichi, JP;

Mitsuru Tamaki, Aichi, JP;

Yukihiro Kimura, Aichi, JP;

Inventors:

Sumio Ohta, Aichi, JP;

Mitsuru Tamaki, Aichi, JP;

Yukihiro Kimura, Aichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wiring substrate is configured such that a build-up layer is formed only on a front surface (a single side) of a core substrate and such that the distance between a semiconductor device mounted on the front surface thereof and an electronic component mounted on the back surface thereof or incorporated therein behind the back surface is reduced to thereby enhance electrical characteristics of an electrically continuous path therebetween, and whose overall strength is enhanced so as not to be prone to deflection or warpage. The wiring substrate includes a relatively thin first core substratehaving a front surfaceand a back surfacea relatively thick second core substratesuperposed on the back surfaceof the first core substrateand having a through openingformed therein, the first substrateand the through openingdefining a recessand a build-up layer BU formed on the front surfaceof the first core substrateand including wiring layersandand dielectric layersand


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