The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7101224 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 05, 2006

Filed:

Sep. 09, 2003
Applicants:

Jerome P. Dattilo, Cedar Park, TX (US);

Richard J. Scherer, Austin, TX (US);

Inventors:

Jerome P. Dattilo, Cedar Park, TX (US);

Richard J. Scherer, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 13/648 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed herein are backplane interconnect systems that use surface mount technology for mating conductive pins in a header connector to surface mount pads on a printed circuit board. In particular, the interconnect system uses a plurality of conductive pins that are not fully inserted into the body of the header connector, thus allowing them to move during mating with a printed circuit board. In this way, the interconnect system exhibits self-leveling characteristics.


Find Patent Forward Citations

Dattilo, Jerome. (2006). Interconnect system (U.S. Patent No. 7101224). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7101224

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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